Accommodating workload diversity in chip multiprocessors via
Accommodating workload diversity in chip multiprocessors via - Telugu x chat
He is a founder member of the IEEE SMC Society Technical Committee on Enterprise Information Systems (EIS). From 2002 to 2004 he was a vice dean for student affair the Faculty of Computer Science and Inf., Univ. He was awarded with the Highly Commended Award from Emerald Literati Club 2002 for his research on network security.
Conflicts for bus were measured only for request bus. From January 2000 up to September 2001, he joined as Visiting Professor to the Department of Computer Science, University of Connecticut. of Mansoura, Faculty of Computer Science from 1997 up to 1999.On the other hand, increasing number of cores in a CMP places a corresponding increasing demand on the bandwidth requirements of an interconnection network.Both these problems are depicted in Figure 1 which shows that the increasing delay of wires and the increasing number of cores that are utilized on a CMP result in more conflicting requests for a shared bus (Conflicting requests result when a request has to wait in a queue because the bus is currently not available.In this paper, we propose a reconfigurable approach to the design of interconnection networks so that the interconnect could be configured on-demand based on workload characteristics.
Since the interconnection network serves as a communication mechanism between the different memory modules in the system, the interaction of the workload with the memory system has direct implications on the performance of the interconnection network.
The main objective of this paper is to survey and discuss the current power management techniques. in 2013 with an overall grade of excellent with honors from Mansoura University. Professor at Computers Engineering and Control systems Dept.––Faculty of Engineering––Mansoura University, Egypt.
Moreover, it proposes a new technique for power management in multi-core processors based on that survey. Attia is a teaching assistant at Computers and Control Systems Engineering Department, Mansoura University. His main research interests include Computer Architecture and Organization, Heterogeneous Multi-Core Architectures, Power-aware computing and Heterogeneous Parallel Programming.
Similar gains can be achieved also for multithreaded applications as shown by further experiments.
Finally, we present the performance sensitivity of the proposed interconnect architecture on shared memory bandwidth availability.
The workload in both cases consisted of two and eight applications respectively from the SPEC benchmark suite.